Epitaxial chemical vapor deposition is a process for growing a thin layer of material on a semiconductor wafer so that the lattice structure is identical to that of the wafer. Using this process, a layer having different conductivity type, dopant species, or dopant concentration may be applied to the semiconductor wafer to achieve the necessary electrical properties. Epitaxial chemical vapor deposition is widely used in semiconductor wafer production to build up epitaxial layers such that devices can be fabricated directly on the epitaxial layer. For example, a lightly doped epitaxial layer deposited over a heavily doped substrate permits a CMOS device to be optimized for latch up immunity as a result of the low resistivity of the substrate. Other advantages, such as precise control of the dopant concentration profile and freedom from oxygen are also achieved.
Prior to epitaxial deposition, the semiconductor wafer is typically mounted on a susceptor in a deposition chamber. The epitaxial deposition process begins by introducing a cleaning gas, such as hydrogen or a hydrogen and hydrogen chloride mixture, to a front surface of the wafer (i.e., a surface facing away from the susceptor) to pre-heat and clean the front surface of the wafer. The cleaning gas removes native oxide from the front surface, permitting the epitaxial silicon layer to grow continuously and evenly on the surface during a subsequent step of the deposition process. The epitaxial deposition process continues by introducing a vaporous silicon source gas, such as silane or a chlorinated silane, to the front surface of the wafer to deposit and grow an epitaxial layer of silicon on the front surface. A back surface opposite the front surface of the susceptor may be simultaneously subjected to hydrogen gas. The susceptor, which supports the semiconductor wafer in the deposition chamber during the epitaxial deposition, is rotated during the process to ensure the epitaxial layer grows evenly.
Epitaxial delta edge roll-off (DERO) is generally an undesirable effect of epitaxial deposition in that it may negatively affect flatness. DERO varies azimuthally according to the crystal lattice directions in conventional, monocrystalline silicon wafers. Flatness of the wafer may commonly be measured by quantities known as SFQR, SBIR, ROA, ERO, ESFQR, ESFQD and the like. In a conventional (100)-oriented silicon wafer, there are four equidistant points around the circumference of the wafer that correspond to <110> equivalent directions. In conventional wafers, DERO may be largest near certain directions, specifically the <110> directions. On the edge profile, including the edge bevel and a rounded interface between the edge bevel and the lateral surface of the wafer, there are typically exposed surfaces near the (311) orientations. Epitaxial growth on the (311) surfaces of the wafer is hindered by large densities of surface atoms on the (311) planes of the wafer. Accordingly, the gas stream is depleted of silicon precursors to a lesser extent when passing from near the (311) surfaces of the wafer onto the near-edge front and back surfaces of the wafer during processing. The result is enhanced growth rate in the vicinity near the (311) surfaces, which may lead to a large DERO in such areas. Epitaxial DERO on silicon wafers undesirably affects the flatness of the wafer, especially near the edge of the wafer. Thus, there remains a need for a system and method for processing a silicon wafer to reduce variation in DERO.